1. Field of the Invention
The present invention relates to semiconductor structures, and more particularly to package structures.
2. Description of the Related Art
With advances associated with electronic products, semiconductor technology has been widely applied in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emission diodes (LEDs), laser diodes and other devices or chipsets. In order to achieve high-integration and high-speed goals, dimensions of semiconductor integrated circuits continue to shrink. In addition, various package techniques also have been proposed or provided to improve performances of integrated circuits.
FIG. 1A is a top view of a prior art package structure.
Referring to FIG. 1A, a die 110 is mounted over a printed circuit board (PCB) 100. The PCB 100 and the die 110 have square shapes. The PCB 100 has two pairs of parallel edges 101 and 103. The die 110 has two pairs of parallel edges 111 and 113. A plurality of bumps (not shown) are formed over the die 110 for connecting with other die or substrate (not shown). The edges 111 and 113 are parallel to the edges 101 and 103, respectively. In addition, corners 105 of the PCB 100 are aligned with corners 115 of the die 110 along the diagonal direction b1.
By using the package structure shown in FIG. 1A, circuits formed over the die 110 are electrically coupled to electrical routings defined over the PCB 100 via a plurality of bumps (not shown). Accordingly, signals generated from the circuits of the die 110 can be transmitted to the PCB 100 and then to another substrate or PCB (not shown) which is electrically coupled to the PCB 100. However, it is found that the bumps (not shown) formed between the die 110 and the substrate 100 are vulnerable to delamination during reliability tests and may be detached from the package structure during and/or after the reliability tests. The detachment of bumps is generally referred to as “white bumps.”
FIG. 1B is a top view of another prior art package structure.
Referring to FIG. 1B, static random access memories (SRAMs) 130 are mounted at corner regions of a printed circuit board (PCB) 120. A central processing unit (CPU) 140 is mounted at the central region of the PCB 120. The PCB 120, the SRAMs 130 and the CPU 140 have square shapes. The PCB 120 has two pairs of parallel edges 121 and 123. The SRAMs 130 and the CPU 140 have two pairs of parallel edges 131, 133 and 141, 143, respectively. A plurality of bumps (not shown) are formed between the SRAMs 130 and the PCB 120, and between the CPU 140 and the PCB 120 for connecting with another die or substrate (not shown). The edges 131 and 133 are parallel to the edges 121 and 123, respectively. In addition, corners 125 of the PCB 120 are aligned with corners 135 of the die 130 along the diagonal direction.
By the package structure shown in FIG. 1B, circuits formed over the SRAMs 130 and the CPU 140 are electrically coupled to routings defined over the PCB 120. In other words, signals generated from the circuits of the SRAMs 130 and the CPU 140 can be transmitted to the PCB 120 and then to another substrate or PCB (not shown) which is electrically coupled to the PCB 120. The package structure, in which the CPU 140 is rotated and disposed at the center of the PCB 120 has a dimension smaller than that of a structure in which a CPU has edges parallel to edges of the SRAMs 130. However, it is found that the bumps (not shown) formed between the SRAMs 130 and the PCB 120, and/or between the CPU 140 and the PCB 120 are vulnerable to delamination during reliability tests and may be detached from the package structure.
From the foregoing, new package structures are desired.